ASIC Design Flow

1. Market Survey and Specification Extraction: It is one of the important phases during the design cycle. Before the logic design, the team performs the market survey to understand what are the different products of similar type available in the market. Origin of any design idea or product can be realized in the quick time, and product should be excellent in all the aspects that are the major objective of any organization. The excellence in the design and product innovation is objective of many research and development organizations. For example, consider Intel as processor design organization, what they work on the processing capability, low power architecture design, high-speed designs, signal integrity, and more reliability to their chipsets. 

For new idea, finalization of the specification and the architecture of the chip is the primary task and for that the market survey plays an important role. Following the team does during the market survey.

(a) The detailed understanding of the available products
(i) Understanding of functionality, speed, power, and area
(ii) Understanding about the electrical characteristics
(iii) Understanding about the mechanical assembly and packaging
(iv) Understanding about the user interfaces

(b) The volume and cost of product
(c) End customer base
(d) How the new idea can be better as compared to existing products?

The main outcome of all above is to extract the specifications of the product or chip at various levels. Our goal is to work on the functional design of the chip so we will consider the functional specifications.

Let us consider the 32-bit processor what we need is the following!
(a) The operations performed by the processor such as arithmetic, logical, data transfer, branching, and floating point
(b) The complexity of bus interfaces such as address bus and data bus
(c) The performance improvement mechanism such as pipelining and the configuration support
(d) The electrical characteristics of interfaces such as slew, voltage levels, and power
(e) The external interface information and compatibility
(f) The internal storage information and the data computation schemes
(g) The IP availability and their specifications
(h) The technology node for ASIC and the performance
(i) What are the constraints achieved such as area, speed, and power?

By using all above, the specifications of the product can be documented and the team understands the feasibility of the product using few risk and dependability matrix parameters. Consider the parameter as a speed, existing chipset is working on the operating frequency of 400 MHz and technology node is 10 nm then can the desired product can operate at 450 MHz or not?

If answer is no due to the technology library cell characteristics, then the choice can be work on the 400 MHz but with more parallel computational elements or can use the lower technology node such as 7 nm to achieve the 450 MHz operating frequency.

2. Design Planning: The design planning in technical terminology is the architecture and micro-architecture design, but practically with this we need to work on the project planning and chip delivery plan to the market. So broadly concurrent teams of technical, man management, and the delivery will work to accomplish the design task. The project planning is ruled out as per as discussion in this book is concerned. Our objective is to work on the understanding of the specification to have the top-level architecture in place so that we can plan for the logical, physical design and chip manufacturing and test phases.

The specification extraction document is used as input during this phase to get

(a) Architecture design and micro-architecture design
(b) Architecture tweaks to estimate the rough area and the possibility of achieving constraints
(c) Having information about the top-level interfaces and the timing
(d) Can be used to understand about the storage and memory requirements
(e) Useful for the project planning and planning of milestone delivery

We will consider the outcome of the design planning stage as the architecture and micro-architecture evolution to have the better architecture design.

3. Logic Design: The logic design phase of the ASIC is very important as the quality of the RTL design and verification decides about the quality of chip. During the logic design phase, broadly we need to perform the following
(a) RTL design
(b) RTL verification
(c) Synthesis
(d) DFT and scan insertion
(e) Equivalence checking
(f) Pre-layout STA

4. Physical Design and GDSII: The physical design phase of the ASIC is also called as backend design, and the physical design team uses the gate-level netlist as one of the inputs with the technology libraries to get the GDSII. During the physical design phase, broadly we need to perform the following
(a) Floor planning
(b) Power planning
(c) CTS
(d) Place and route
(e) LVS
(f) DRC
(g) Signoff STA
(h) GDSII

5. Chip: To get the chip from foundry, there are several manufacturing and packaging processes. The sample chips will be issued to test houses to perform the testing.

© Springer Nature Singapore Pte Ltd. 2021
V. Taraate, ASIC Design and Synthesis,
https://doi.org/10.1007/978-981-33-4642-0_2